The need to reduce transistor size is a perennial problem to be solved in the art of integrated circuits. One way that the Background Art reduced transistor size was to reduce the length of the channel. Doing so effectively reduced the overall footprint of the transistor. But then a minimum channel length (relative to other physical parameters of the transistor) was achieved below which problems were created, e.g., short channel effects.
The Background Art responded by developing a transistor architecture that reduced the transistor's footprint size while maintaining at least the minimum channel length. Whereas the larger footprint transistor architecture used a planar channel, the smaller footprint transistor architecture used a folded channel.
FIG. 9 is a three-quarter perspective view of the smaller footprint architecture according to the Background Art, which is generally referred to as a FinFET and particularly here as a triple-channel FinFET 900 having a body 902 (in which is formed the channel) in the shape of a fin (obscured in FIG. 9 but see 902b in FIG. 10) formed on a buried oxide (BOX) structure 901 between a source region 902a and a drain region 902C. Gate electrode 906 conforms (as does interposed gate oxide layer 904) to the shape of body 902.
FIG. 10 is a cross-sectional view of Background Art FinFET 900 taken along line X–X′ of FIG. 9. Recall that the inversion layer induced in a channel is located in body 902 next to gate oxide 904 and tends to be rather shallow. An idealized effect of gate electrode 906 being adjacent to three sides of body 902 is as if three separate inversion layers are induced, namely a first inversion layer 908a, a second inversion layer 908b and a third inversion layer 908C. Hence, FinFET 900 can be referred to as a triple-channel FinFET.
Continuing efforts to reduce transistor size has led to the multi-bridge-channel FET (MBCFET). An MBCFET can be described as an FET having a stack of quadruple-channel bridges. FIGS. 1A and 1B are perspective views showing an active pattern and a gate electrode of an NMOS or PMOS MBCFET according to the Background Art.
Referring to FIG. 1A, an active pattern formed on a surface of an integrated circuit substrate such as a semiconductor substrate (not shown) includes a bridge-region 1 having plurality of bridges 4a, 4b and 4c formed in a vertical direction. Multiple channels can be induced in each bridge 4a, 4b and 4c of an operational MBCFET.
A plurality of tunnels 2a, 2b and 2c are formed between bridges 4a, 4b and 4c. Source/drain regions 3 are formed at the both sides of the bridge-region 1 (or, in other words, a central portion of the active pattern) so as to be connected to the plurality of bridges 4a, 4b and 4c (and the channels induced therein). Source/drain regions 3 are formed to have a width wider than that of bridges 4a, 4b and 4c. Between source/drain regions 3 and bridges 4a, 4b, 4c, there may be formed source/drain extension layers 5 connecting source/drain regions 4 to bridges 4a, 4b and 4c. 
The plurality of tunnels 2a, 2b and 2c are formed between the bridges 4a, 4b and 4c. The lowest tunnel 2a is formed between the lowest bridge layer 4a and the underlying surface portion of the semiconductor substrate. A groove 2′ corresponding in shape to tunnels 2a, 2b and 2c of a tunnel shape is formed on the uppermost bridge 4c. 
Referring to FIG. 1B, a gate electrode 6 is formed on the active pattern. A gate-insulating layer 7 is formed between gate electrode 6 and the plurality of bridges 4a, 4b and 4c. Gate electrode 6 extends through and/or fills up the plurality of tunnels 2a, 2b and 2c and tunnel groove 2′. As such, gate electrode 6 is formed to surround the plurality of bridges 4a, 4b and 4c. 
During operation, an MBCFET gate electrode 6 can induce four channels in each of bridges 4a, 4b and 4c. More particularly, an idealized effect of gate electrode 6 being adjacent to four sides of one of the brides 4a, 4b and 4c is as if four inversion layers (channels) are induced in the bridge. The four inversion layers are analogous to inversion layers 908a, 908b and 908c in FIG. 10.
Returning to FIG. 1A, before tunnels 2a, 2b and 2c are formed, the precursor to bridge-region 1 of the active pattern includes not only the plurality of bridge layers 4a, 4b and 4c (in which will be induced corresponding channels) but also a plurality of interbridge layers (which will become tunnels 2). The bridge and interbridge layers are stacked alternately with each other. Bridges 4a, 4b and 4c can include a single crystalline semiconductor film, such as silicon (Si) film. The interbridge layers can include silicon-germanium (SiGe). To obtain the arrangement of bridges 4a, 4b and 4c and tunnels 2a, 2b and 2c in FIG. 1A, the precursor to bridge-region 1 of the active pattern is etched with an etchant that is selective to SiGe over Si. In other words, such an etchant is used to form tunnels 2a, 2b and 2c. 